1. Field of the Invention
This invention is directed to a novel process of fabricating indium phosphide junction field-effect transistors (JFETs) and indium phosphide junction high electron mobility transistors (JHEMTs) and more particularly to such processes which utilize a nitride-registered gate approach to obtain JFETs and JHEMTs having sub-micron gate lengths.
2. Background Description
In the past, Indium Phosphide(InP) JFETs have been fabricated using both Zn-diffused and Be ion-implanted approaches. Though respectable gain and power performance has been achieved from devices with 1.5 .mu.m gate lengths or longer, stringent demands on the fabrication process have impeded the attainment of shorter gate lengths.
The major difference between a JFET and a MESFET is that the gate of a JFET is controlled through the use of a p-n junction whereas in a MESFET a Schottky barrier is employed. Accordingly, two requirements of a JFET which are not present in a MESFET is that a p.sup.+ region must be formed and a high quality ohmic contact must be made to this p.sup.+ region. This dual requirement complicates the fabrication of JFETs when coupled with the fact that for high frequency performance the length of this p.sup.+ region must be one micron or less.
Previous fabrication approaches have employed either vapor-phase epitaxy, blanket or selective diffusion, and blanket or selective ion-implantation to form the p.sup.+ region of the JFET. The non-selective approaches incur problems with the removal of the excess p.sup.+ material which is not directly beneath the gate metal. This p.sup.+ removal process must satisfy a number of different requirements including the use of a highly selective, highly controlled etching procedure which does not adversely affect the p-type metallization, the p-type contact resistance or the JFET transconductance and gate-drain breakdown voltage. A major problem is the necessity that the etch process be of sufficient control to enable stopping at the lower p.sup.+ /n interface. Compounding the problem is that, instead of obtaining the desired etch front profile, a rounded or spiked profile may occur due to preferential etching near the mask edges. Terminating the etch prior to reaching the interface results in undesirably long gate lengths. Overetching results in transconductance compression since in this case a significant fraction of the gate voltage is used to deplete electrons beneath the channel current, which prior to overetching was constricted by the bottom of the p/n junction, is now constricted by the depletion region formed under the overetched recesses on either side of the gate. Adding to the difficulty of end-point detection is the further complication of the delecterious effects on device performance due to etched surfaces in close proximity to the modulation area.
Designs employing solely a selectively diffused p.sup.+ region are limited by the lateral diffusion of the p-type dopant beneath the dielectric mask which hinders the attainment of a 1.0 .mu.m or less p.sup.+ gate length.
Designs employing solely a selectively implanted, 1.0 .mu.m p.sup.+ region are constrained by the requirement of implant registration which must be maintained through the 700.degree.-850.degree. C. activation anneal, and the necessity that the gate metallization be deposited solely within that implanted p-type region. Implanting an initially oversized 2.0-3.0 .mu.m p.sup.+ region relaxes the difficulty of the 1.0 .mu.m gate metal alignment, but introduces the additional problems associated with the removal of the excess p.sup.+ material which was previously mentioned.